Pixel binning is a clocking scheme used to combine the charge collected by several adjacent CCD pixels, and is designed to reduce noise and improve the signal-to-noise ratio and frame rate of digital cameras. The binning process is performed by on-chip CCD clock timing circuitry that assumes control of the serial and parallel shift registers prior to amplification of the CCD analog signal.

To help illustrate the pixel binning process, refer to Figure 1, which reviews an example of 2 x 2 binning. A schematic drawing of a 4 x 4 parallel shift register pixel array is illustrated in Figure 1(a), along with a four-gate serial shift register and summing pixel or well (also termed an output node). Illuminating photons impact the CCD photodiodes, creating a pool of electrons that accumulates in each pixel, shown in Figure 1(b) as a cluster of four blue-shaded squares in the upper right hand corner of the parallel shift register. The number of electrons that each pixel can accommodate is termed the well depth and ranges from about 30,000 to 350,000, depending upon the CCD specifications. Dynamic range of a CCD is directly proportional to the well depth. Incident light levels and exposure time determine the number of electrons collected at each photogate or pixel site. After exposure of the CCD to one illumination cycle is completed, the electrons are transferred through the parallel and serial shift registers to a output amplifier and then digitized by an analog-to-digital (A/D) converter circuit. Binning can be used to increase focusing accuracy by reducing the time necessary for image acquisition, while providing greater sensitivity to lower out-of-focus light levels.

To illustrate this process, Figure 1(b) shows each integrated pixel in the parallel register stepping by an increment of one gate to yield the arrangement shown in Figure 1(c). Here, the electrons from two pixels remain in the parallel shift register, while those from the other two have been transferred to the serial shift register. Another step (Figure 1(c)), shifts the remaining electrons in the parallel shift register to fill the adjacent gate elements in the serial register (Figure 1(d)). The final steps involve shifting of charge from the serial register, two pixels at a time, to the summing pixel (Figure 1(d) and (e)). Figure 1(f) illustrates the combined charge of four pixels in the summing well awaiting transfer to the output amplifier, where the signal will be converted to a voltage and then transferred to other integrated circuits for further amplification and digitization. The process continues until the entire array has been read out. In this example, the area of four adjacent pixels has been combined into one larger pixel, sometimes referred to as a super pixel. The signal-to-noise ratio has been increased by a factor of four, but the image resolution is cut by 50 percent.

	Interactive Tutorial
CCD Pixel Binning Discover how CCD clock cycles can be modified to combine charge from adjacent pixels during readout in order to improve signal-to-noise at the expense of spatial resolution.

Binning array sizes are controlled by the CCD clock, bias voltages, and video processing signal timing, and are usually adjustable from 2 x 2 pixels to a maximum that can include almost the entire CCD array. However, in the binning mode, both the serial shift register and output node will accumulate a significantly larger charge than in normal operation and must contain sufficient electron charge capacity to prevent saturation. Typical CCD serial registers have twice the charge capacity as the parallel registers, and the output nodes usually contain 50- to 100-percent more charge capacity than do the shift registers. As an example, the Kodak KAF full-frame CCD image sensors have a parallel array of 9-micron pixels, each with a capacity of 120,000 electrons. The KAF serial registers have an electron capacity twice that of the parallel registers (240,000 electrons), while the output node has a capacity of 330,000 electrons.

The primary benefit of pixel binning is to improve the signal-to-noise ratio in low light conditions at the expense of spatial resolution. Summation of many charge packets reduces the read noise level and produces an improvement in signal equal to the binning factor (4x in the example above). Dark current noise is not reduced by binning and may only be overcome by cooling the CCD to low temperatures. Binning is useful in a variety of applications, especially where fast throughput times (frame rates) are desired at the expense of resolution.

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