Caches are static memory on a chip to keep program instructions and data with the highest probability to be executed in the near future. The unique feature of 21164 is that has primary and secondary cache on the chip.

The size of PIC (primary instruction cache) is 8 KB*, which means that it can hold approximately 1,000 instructions. The size of data cache is also 8 KB. The size of the secondary cache is 96 KB and this cache keeps instructions and data.

* K - kilo - 1024; Byte - 8 bits of binary data; 8KB is 8192 Bytes; is 65,536 bits

The idea behind the cache is ability to have the fastest overall instruction execution. To achieve the fastest instruction execution, there is an obvious need to fastest possible access to instructions and data.

To achieve the trade off between fastest possible execution and the overall cost of the computer system, each computer today employs similar memory hierarchy:

Media Capacity Speed CD disk 650 MB 100 ms hard disk 2 GB 8 ms main memory 32 MB 60 ns off-chip cache 96 MB 40 ns on-chip cache 8 KB 20 ns on-chip registers 120 2 ns

Above numbers are typical and approximate for the today average new PC home computer. As we can see there is a wide spectrum of capacities, speed and cost for different media.

The idea of a memory cache is similar to the money. We keep coins usually in pocket, paper money - cache in valet and bigger money in the bank. We have fastest access to money in pocket and valet. To access money in bank, it takes some time driving and standing in line.

To execute the next set of instruction, microprocessor logic first looks into the primary cache. If the logic finds valid instructions to be executed, it grabs them and places in the queue for execution. If logic can not find valid instructions it looks into the secondary cache. If can not find them in the secondary cache it puts the request to the operating system to look into of-the chip cache and eventually into the main memory and finally into the hard disc.

The caches are arrays of cells plus additional logic to address the cells. Arrays are organized in different aspect ratios to satisfy available chip floor plan and achieve the fastest possible access speed.

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