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Integrated Circuit Image Gallery

Texas Instruments 486DX4 Microprocessor

Despite the name, the Texas Instruments 486DX4 microprocessor does not run internally at four times the memory bus speed, but rather at triple the external clock speed. Since Intel reserved the DX3 designation for a 2.5 times clock multiplier that never reached the marketplace, they created the newer moniker, the DX4, which other licensees such as IBM, AMD, SGS, and Cyrix also adopted. Although Intel never produced one, clone makers such as Advanced Micro Devices (AMD) and Cyrix sold 5x86 processors that were actual clock quadruplers.

View a low magnification image of the ti486DX4 processor.

View a medium magnification image of the ti486DX4 processor.

Responding to competitive pressures and advancing silicon fabrication process techniques, Intel continued to release faster and more powerful 486DX4 chips in the late 1980s and early 1990s. After their initial 50 MHz clock speed 486 chip in 1989, the DX2 at 66 MHz clock speed in 1992, and the first 486DX4s at 75 MHz clock speeds in 1994, Intel shipped the 486DX4-100 MHz processors with a write-back memory cache in 1996. Other advances included reducing the waste power dissipation from a typical 3.7 watts down to a more acceptable 2.8 watts. The reduced voltage requirements permitted the 486DX4 chips to match new battery-powered laptop personal computers and to garner favor as environmentally friendly "green machines". Texas Instruments licensed the manufacturing of these improved microprocessors in the 486 family and produced 75-MHz through 100-MHz clock versions of the 486DX4.

The TI 486DX4 featured an 8-kilobyte cache memory initially, followed by 16 kilobytes that matched slower memory systems while yielding a 25 percent gain in overall performance. In 1996, Texas Instruments manufactured a custom clock-doubled 100-MHz DX4 for its notebook division. The processor was coupled with a faster 50-MHz system board while most 486-class systems, including TI Model 450 notebook computers, used a 25- or 33-MHz bus that created a computing bottleneck.

Contributing Authors

Omar Alvarado, Thomas J. Fellers and Michael W. Davidson - National High Magnetic Field Laboratory, 1800 East Paul Dirac Dr., The Florida State University, Tallahassee, Florida, 32310.


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