The Half Adder

The Half Adder

This chip is the "half-cousin" to the Full Adder Hewlett-Packard integrated circuit that features a complete snake (the "Full Adder"). The "Half Adder" is seen in the lower section of the photomicrograph in the pad ring. In digital logic design, the Half Adder and Full Adder are two fundamental circuits for performing addition of binary numbers. A full adder takes in three binary bits and produces two bits: sum and carry. The slightly simpler half adder takes in two bits and produces two bits. Officially, the chip is termed the Addchilada 32/64 Bit Floating Point Add/Sub math chip and was used in the venerable HP 1000 minicomputer. The chip was invented by HP Cupertino designers Fred Ware and Howard Shishido in 1979. Todd Johnson of Santa Cruz, California was kind enough to donate a wafer of these Silicon-On-Sapphire (SOS) chips to the Silicon Zoo.

Paul Koning of Xedia Corporation has amused us with a nice little anecdote about the Adder snake:

The waters of the Great Flood were receding, and Noah had beached his Ark. The animals were leaving, and he sent them off with the words:

"Go forth and multiply."

Then he heard a plaintive voice from below:

"We can't -- we're Adders."

Looking down, Noah saw the two snakes, slithering off. A month or two later, Noah was wandering about, looking to see how all the creatures were doing. To his surprise and delight, he came across the adders, with a nest full of little ones. He said to them:

"I thought you told me you couldn't multiply?"

They replied:

"We used logarithms."


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